The present invention relates generally to integrated circuits and in particular the present invention relates to internal signal communication via integrated circuit interconnects.
Integrated circuit devices are fabricated with numerous internal circuits which require internal communication throughout the device. These circuits are coupled using interconnect lines, such as a patterned metal layer. Traditionally, integrated circuit interconnect lines required a relatively small percentage of an integrated circuit die area. Integrated circuits, however, are becoming more densely populated as the area required to fabricate transistors is reduced. Thus, as circuit density increases, the proportionate area required for the interconnect lines increases relative to the area required for circuitry. In addition, as the complexity of the integrated circuit continues to increase, the need for additional interconnect lines also increases.
One type of integrated circuit which has complex interconnect lines are switching, or routing devices. These integrated circuit routing devices operate as sophisticated multiplex circuitry to route numerous input connections to numerous output connections. These routing devices, often used in communication systems, require complex internal interconnect routing which could benefit from a reduction in the number of interconnect lines.
To increase data communication bandwidth between integrated circuits using a limited number of external connections, double pumped circuitry has been used in combination with clock multiplier circuits. The double pumped circuitry allows data to be transmitted between the integrated circuit devices at increased speeds compared to a system clock. For example, a clock multiplier which doubles the system clock can be provided to increase data between integrated circuits by a factor of two. This technique has been limited to external communications between integrated circuits to reduce the number of external package connections, and is not an attractive option for internal communication because of the need for clock multiplier circuits. For the reasons stated above, there is a need in the art for circuitry which relieves routing congestion within integrated circuits without requiring clock multiplier circuits.
In one embodiment, integrated circuit interconnect circuitry is described which comprises a transmitter circuit and a receiver circuit. The transmitter includes a first flip-flop circuit adapted to receive a first input signal, a second flip-flop circuit adapted to receive a second input signal, and logic circuitry. The logic circuitry is coupled to the first and second flip-flop circuits to transmit an interconnect signal comprising the first and second input signals on an interconnect line. The receiver circuit is coupled to the interconnect line and comprises a third flip-flop circuit adapted to receive the interconnect signal and provide a first output signal corresponding to the first input signal, and a fourth flip-flop circuit adapted to receive the interconnect signal and provide a second output signal corresponding to the second input signal.
In another embodiment, an integrated circuit comprises a first internal circuit in electrical communication with a second internal circuit via interconnect circuitry. The interconnect circuitry includes a transmitter circuit which receives multiple input signals and provides a single output signal on a first interconnect line in response to a clock signal. The single output signal comprising portions of the multiple input signals. A repeater circuit is provided which receives the single output signal on the first interconnect line and re-transmits the single output signal on a second interconnect line. A receiver circuit is also provided which receives the single output signal on the second interconnect line and separates the single output signal into the multiple input signals in response to the clock signal.
In yet another embodiment, a method of reducing integrated circuit interconnect routing is described. The method comprises latching a first internal data signal in response to a rising edge of a system clock, latching a second internal data signal in response to a falling edge of the system clock, and transmitting the first internal data signal and the second internal data signal on an interconnect line as a composite signal. The first internal data signal is transmitted on the interconnect line when the system clock is in a high state, and the second internal data signal is transmitted on the interconnect line when the system clock is in a low state. The method also comprises receiving the composite signal transmitted on the interconnect line, and separating the composite signal into first and second internal output data signals.
An integrated circuit interconnect transmitter/repeater circuit is described which comprises a rising edge triggered latching circuit having an input connection and an output connection. A signal provided on the input connection is coupled to the output connection in response to a rising edge of a clock signal. A falling edge triggered latching circuit is provided which has an input connection and an output connection, such that a signal provided on the input connection is coupled to the output connection in response to a falling edge of the clock signal. A logic circuit is coupled to the output connections of the rising edge triggered latching circuit and the falling edge triggered latching circuit. The logic circuit provides a composite output signal comprising an output signal from the rising edge triggered latching circuit during one-half of the clock signal cycle, and an output signal from be falling edge triggered latching circuit during a second half of the clock signal cycle.